V K Surya is pursuing Ph.D. degree in School of Electrical Science, Indian Institute of Technology (IIT) Bhubaneswar, Odisha, India. He received his integrated B. Tech and M.Tech (dual degree) from School of Minerals, Metallurgical and Materials Engineering, IIT Bhubaneswar. His research is focused on analog CMOS circuit design for high-speed serial links.
Email: s24ec09001@iitbbs.ac.in
Publications
- V. K. Surya, S. K. Prusty, B. D. Sahoo and N. Wary, “Energy Efficient Resistor-Transconductor Hybrid-Based Full-Duplex Transceiver for Serial Link,” in IEEE Transactions on Circuits and Systems I: Regular Papers, 2024 (accepted for publication)
- V. K. Surya, Suraj Kumar Prusty and N. Wary, “A 26 Gb/s Echo-Cancellation Based Simultaneous Bidirectional Transceiver in 65 nm CMOS”, IEEE International Symposium on Circuits & Systems, Monterey, California, 2023.
- S. K. Prusty, S. P. Dash, V. K. Surya and N. Wary, “Differential Evolution-Based Adaptation Algorithm for Multistage Continuous-Time Linear Equalizer,” in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 13, no. 12, pp. 2046-2049, Dec. 2023.
- S. K. Prusty, V. K. Surya and N. Wary, “Energy Efficient Integrated Summer and Latch-Based DFE With Reduced Tap Loading,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 4, pp. 1779-1783, April 2024
- Suraj Kumar Prusty, V. K. Surya and N. Wary, “A High-Speed Charge-Injection based Double Tail Latch for Decision Feedback Equalizer (DFE)”, 21st IEEE Interregional NEWCAS Conference, Edinburgh, Scotland, June 2023.
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