Journal Publications

  • X. Mo, J. Wu, N. Wary and T. C. Carusone, “Design Methodologies for Low-Jitter CMOS Clock Distribution,” in IEEE Open Journal of the Solid-State Circuits Society, vol. 1, pp. 94-103, 2021 [IEEExplore]
  • B. Vatankhahghadim, N. Wary, J. Bailey and A.Chan Carusone, “A Study of Discrete Multitone Modulation for Wireline Links Beyond 100 Gb/s”, IEEE Open Journal of Circuits and Systems, vol. 2, pp. 78-90, 2021. [IEEExplore]
  • N. Wary, A. R. Chowdhury and P. Mandal, “Hybrid Bidirectional Transceiver for Multipoint-to-Multipoint Signaling Across On-Chip Global Interconnects”, IET Circuit, Devices and System, Vol.14, Issue 6, pp. 780-787, Sept. 2020. [IEEExplore]
  • B. Dehlaghi, N. Wary and A.Chan Carusone, “Ultra-Short-Reach Interconnects for Die-to-Die Links”, IEEE Solid-State Circuits Magazine, vol. 11, no. 2, pp. 42-53, Spring 2019. [IEEExplore]
  •  N. Wary and P. Mandal, “Current-Mode Full-Duplex Transceiver for Lossy On-Chip Global Interconnects”, IEEE Journal of Solid-State Circuits, vol. 52, no. 8, pp. 2026-2037, Aug. 2017. [IEEExplore]
  • N. Wary and P. Mandal, “Current-Mode Triline Transceiver for Coded Differential Signaling Across On-Chip Global Interconnects”, IEEE Transactions on Very Large Scale Integration, vol. 25, no. 9, pp. 2575-2587, Sept. 2017. [IEEExplore]
  • N. Wary and P. Mandal, “High Speed Energy Efficient Bi-directional Transceiver for On-Chip Global Interconnects”, IET Circuit, Devices and System, Vol.9, Issue 5, pp. 319-327, Sept. 2015. [IEEExplore]
  • N. Wary and P. Mandal, “A low impedance receiver for power efficient current mode signalling across on-chip global interconnects”, International Journal Electronic and Communication, Elsevier, Vol. 68, No. 10, pp. 969-975, Oct 2014.  [Link]

Conference Publication

  • B. Vatankhahghadim, N. Wary and A.Chan Carusone, “Discrete Multitone Signalling for wireline Communication”, IEEE International Symposium on Circuits & Systems, Seville, Spain, Oct 12-14, 2020.  [IEEExplore]
  • P. Chen, N. Wary and A.Chan Carusone,”All-Digital Calibration Algorithms to Correct for Static Non-Linearities in ADCs”, IEEE International Symposium on Circuits & Systems, Seville, Spain, Oct 12-14, 2020. [IEEExplore]
  • A. R. Chowdhury, N. Wary and P. Mandal, “A Regulated-Cascode Based Current-Integrating TIA RX with 1-Tap Speculative Adaptive DFE”, 2019 62nd IEEE International Midwest Symposium on Circuits and Systems, Dallas, TX, USA, 2019, pp. 790-793. [IEEExplore]
  • A. R. Chowdhury, N. Wary and P. Mandal, “Energy Efficient Bidirectional Equalized Transceiver with PVT Insensitive Active Termination”, 2019 32th International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID), Delhi, Jan 2019, pp.25-30. [IEEExplore]
  • N. Wary and P. Mandal,”Current-Mode Simultaneous Bidirectional Transceiver for On-Chip Global Interconnects”, Quality Electronic Design (ASQED), 2015 6th Asia Symposium on,Kuala Lumpur, Aug. 2015, pp. 19-24. [IEEExplore]


  • X. Mo, N. Wary, and A. Chan Carusone, “High-Performance CMOS Clock Distribution,”  in Phase-Locked Frequency Generation and Clocking: Architectures and circuits for modern wireless and wireline systems, Editor W. Rhee, The Institution of Engineering and Technology, 2020. [Link]

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