To meet the ever-increasing demand of global data traffic arising from Youtube, Netflix, Google, Facebook, etc., the Hybrid Memory Cube (HMC) specification and High-Bandwidth Memory standard call for an aggregate bandwidth of 8 Tb/s in next-generation memory-to-processor links. At the same time, the data rates processed by individual line cards in data center switches will soon go beyond 25 Tb/s. However, as the data rate of serial links over copper interconnects increases, the links appear highly lossy. Further, the power consumption of a wireline transceiver, including all clocking and equalization circuits, increases. Publications suggest a tenfold increase in power consumption with a 30-dB increase in channel loss. Hence, energy-efficient communication equipment should be engineered to keep the channel loss as low as possible. Everyday, tens of gigawatt hours  electricity is consumed by these links in the data servers. So, an attempt of saving even a fraction of power in these links can save a significant portion of the total global power consumption.

The work in this project involves analog CMOS circuit design, layout design and sending the prototype chip for fabrication. In the process, the students will get an exposure to the industry standard IC design tools and get an experience of the entire chip design flow.


  • Title: High-speed and energy efficient CMOS transceiver design for full-duplex chip-to-chip serial link
    • Funding Agency: DST-SERB
    • Duration: 2 years
    • Type: Sponsored Research

  • Title: Analog Design for Serial Link