Suraj Kumar Prusty is pursuing Ph.D. degree in Indian Institute of Technology (IIT) Bhubaneswar, Odisha, India. He received his M.Tech. degree with the specialisation of VLSI Design and Embedded Systems from National Instititute of technology (NIT) Rourkela, Odisha and B.Tech. degree from Silicon Institute of Technology, Bhubaneswar. His research is focused on analog CMOS circuit design for high-speed serial links.
Email: skp23@iitbbs.ac.in
Publications
- Suraj Kumar Prusty, V. K. Surya and N. Wary, “Energy Efficient Integrated Summer and Latch Based DFE With Reduced Tap Loading”, IEEE Transactions on Circuits and Systems II, vol. 71, no. 4, pp. 1779-1783, April 2024.
- Suraj Kumar Prusty, S. P. Dash, V. K. Surya, and N. Wary, “Differential evolution based adaptation algorithm for multi-stage continuous time linear equalizer,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 13, no. 12, pp. 2046-2049, Dec. 2023.
- Suraj Kumar Prusty, V. K. Surya and N. Wary, “A High-Speed Charge-Injection based Double Tail Latch for Decision Feedback Equalizer (DFE)”, 21st IEEE Interregional NEWCAS Conference, Edinburgh, Scotland, June 2023.
- V. K. Surya, Suraj Kumar Prusty, B. D. Sahoo and N. Wary, “Energy Efficient Resistor-Transconductor Hybrid-Based Full-Duplex Transceiver for Serial Link,” in IEEE Transactions on Circuits and Systems I: Regular Papers, 2024 (accepted for publication)
- V. K. Surya, Suraj Kumar Prusty and N. Wary, “A 26 Gb/s Echo-Cancellation Based Simultaneous Bidirectional Transceiver in 65 nm CMOS”, IEEE International Symposium on Circuits & Systems, Monterey, California, 2023.
- P. Chandrika Kondeti, Suraj Kumar Prusty and N. Wary, “Current-Integrating Summer for DFE Receiver With Low Common Mode Variation”, Microelectronics Journal, Elsevier, Vol. 123, May 2022.
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