Publications

Journal Publications

  1. S. K. Prusty, V. K. Surya and N. Wary, “Energy Efficient Clock-Based Summer-Latch for Delay Reduction in DFE-Based Receiver,” in IEEE Transactions on Circuits and Systems I: Regular Papers. (accepted)
  2. Suraj Kumar Prusty, V.K. Surya, N. Wary, “Energy-efficient summer with enhanced bandwidth for decision feedback equalizer”, AEU – International Journal of Electronics and Communications, Vol. 203, Jan 2026, (accepted)
  3. P. K. Govindaswamy, N. Wary and V. S. Pasupureddi, “A 0.0375-pJ/bit Charge-Steering Based Hybrid for 8-Gb/s/pin Full-Duplex Chip-to-Chip Interconnects in 65-nm CMOS,” in IEEE Transactions on Circuits and Systems I: Regular Papers, doi: 10.1109/TCSI.2024.3469395. (accepted)
  4. V. K. Surya, S. K. Prusty, B. D. Sahoo and N. Wary, “Energy Efficient Resistor-Transconductor Hybrid-Based Full-Duplex Transceiver for Serial Link,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no. 12, pp. 6569-6581, Dec. 2024.[IEEExplore]
  5. S. K. Prusty, V. K. Surya and N. Wary, “Energy Efficient Integrated Summer and Latch-Based DFE With Reduced Tap Loading,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 4, pp. 1779-1783, April 2024 [IEEExplore]
  6. S. K. Prusty, S. P. Dash, V. K. Surya and N. Wary, “Differential Evolution-Based Adaptation Algorithm for Multistage Continuous-Time Linear Equalizer,” in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 13, no. 12, pp. 2046-2049, Dec. 2023. [IEEExplore]
  7. P. Chandrika Kondeti, Suraj Kumar P. and N. Wary, “Current-Integrating Summer for DFE Receiver With Low Common Mode Variation”, Microelectronics Journal, Elsevier, Vol. 123, May 2022. [Link]
  8. X. Mo, J. Wu, N. Wary and T. C. Carusone, “Design Methodologies for Low-Jitter CMOS Clock Distribution,” IEEE Open Journal of the Solid-State Circuits Society, vol. 1, pp. 94-103, 2021 [IEEExplore]
  9. B. Vatankhahghadim, N. Wary, J. Bailey and A.Chan Carusone, “A Study of Discrete Multitone Modulation for Wireline Links Beyond 100 Gb/s”, IEEE Open Journal of Circuits and Systems, vol. 2, pp. 78-90, 2021. [IEEExplore]
  10. N. Wary, A. R. Chowdhury and P. Mandal, “Hybrid Bidirectional Transceiver for Multipoint-to-Multipoint Signaling Across On-Chip Global Interconnects”, IET Circuit, Devices and System, Vol.14, Issue 6, pp. 780-787, Sept. 2020. [Link]
  11. B. Dehlaghi, N. Wary and A.Chan Carusone, “Ultra-Short-Reach Interconnects for Die-to-Die Links”, IEEE Solid-State Circuits Magazine, vol. 11, no. 2, pp. 42-53, Spring 2019. [IEEExplore]
  12.  N. Wary and P. Mandal, “Current-Mode Full-Duplex Transceiver for Lossy On-Chip Global Interconnects”, IEEE Journal of Solid-State Circuits, vol. 52, no. 8, pp. 2026-2037, Aug. 2017. [IEEExplore]
  13. N. Wary and P. Mandal, “Current-Mode Triline Transceiver for Coded Differential Signaling Across On-Chip Global Interconnects”, IEEE Transactions on Very Large Scale Integration, vol. 25, no. 9, pp. 2575-2587, Sept. 2017. [IEEExplore]
  14. N. Wary and P. Mandal, “High Speed Energy Efficient Bi-directional Transceiver for On-Chip Global Interconnects”, IET Circuit, Devices and System, Vol.9, Issue 5, pp. 319-327, Sept. 2015. [Link]
  15. N. Wary and P. Mandal, “A low impedance receiver for power efficient current mode signalling across on-chip global interconnects”, International Journal Electronic and Communication, Elsevier, Vol. 68, No. 10, pp. 969-975, Oct 2014.  [Link]

Conference Publication

  1. S. R. Kariveda, S. K. Prusty and N. Wary, “Machine Learning based Adaptation for CTLE of Serial Links,” 2024 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Taipei, Taiwan, Dec. 2024, pp. 95-99
  2. Soumojit Bakshi, V K Surya and N. Wary,”Pin Efficient Tri-Level based Inductive Coupling Transceiver for 3D ICs”, 2024 38th International Conference on VLSI Design and 2025 24th International Conference on Embedded Systems (VLSID), Banglore, India, Jan 4-8, 2025.
  3. K. Sujal Reddy, Suraj Kumar P. and N. Wary, “Machine Learning Based Adaptation for CTLE of Serial Links”, 2024 IEEE Asia Pacific Conference on Circuits and Systems, Taipei, Taiwan, November 7-9, 2024. [IEEExplore]
  4. J. Singh, N. Wary and P. Mandal, “Use of current-mode and voltage-mode receivers together for on-chip multipoint-to-multipoint data transmission across global interconnects,” 2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID), Kolkata, India, 2024, pp. 73-78.[IEEExplore]
  5. Sahil Dalvi, Pilli Kalyan Kumar, Olive Ray and N. Wary, “A Fully Integrated SCC DC-DC Converter with Novel FMC Controller for Fast Transient Response”, 21st IEEE Interregional NEWCAS Conference, Edinburgh, Scotland, June 2023. [IEEExplore]
  6. Suraj Kumar P., V. K. Surya and N. Wary, “A High-Speed Charge-Injection based Double Tail Latch for Decision Feedback Equalizer (DFE)”, 21st IEEE Interregional NEWCAS Conference, Edinburgh, Scotland, June 2023. [IEEExplore]
  7. V. K. Surya, Suraj Kumar P. and N. Wary, “A 26 Gb/s Echo-Cancellation Based Simultaneous Bidirectional Transceiver in 65 nm CMOS”, IEEE International Symposium on Circuits & Systems, Monterey, California, 2023. [IEEExplore]
  8. Nishant Maurya and N. Wary, “Design and Analysis of PVT Invariant Current Reference in 65-nm CMOS” 65th IEEE International Midwest Symposium on Circuits and Systems, Fukuoka, Japan, 2022. [IEEExplore]
  9. Prema Kumar G., N. Wary and Vijaya Sankara Rao P., “Power Efficient Echo-Cancellation Based Hybrid for Full-Duplex Chip-to-Chip Interconnects”, IEEE International Symposium on Circuits & Systems, Texas, Austin, 2022. [IEEExplore]
  10. Prema Kumar G., N. Wary and Vijaya Sankara Rao P., “Low-Power Half-Rate Charge-Steering Hybrid for Full-Duplex Chip-to-Chip Interconnects”, IEEE International Symposium on Circuits & Systems, Texas, Austin, 2022. [IEEExplore]
  11. B. Vatankhahghadim, N. Wary and A. Chan Carusone, “Discrete Multitone Signalling for wireline Communication”, IEEE International Symposium on Circuits & Systems, Seville, Spain, Oct 12-14, 2020.  [IEEExplore]
  12. P. Chen, N. Wary and A.Chan Carusone,”All-Digital Calibration Algorithms to Correct for Static Non-Linearities in ADCs”, IEEE International Symposium on Circuits & Systems, Seville, Spain, Oct 12-14, 2020. [IEEExplore]
  13. A. R. Chowdhury, N. Wary and P. Mandal, “A Regulated-Cascode Based Current-Integrating TIA RX with 1-Tap Speculative Adaptive DFE”, 2019 62nd IEEE International Midwest Symposium on Circuits and Systems, Dallas, TX, USA, 2019, pp. 790-793. [IEEExplore]
  14. A. R. Chowdhury, N. Wary and P. Mandal, “Energy Efficient Bidirectional Equalized Transceiver with PVT Insensitive Active Termination”, 2019 32th International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID), Delhi, Jan 2019, pp.25-30. [IEEExplore]
  15. N. Wary and P. Mandal,”Current-Mode Simultaneous Bidirectional Transceiver for On-Chip Global Interconnects”, Quality Electronic Design (ASQED), 2015 6th Asia Symposium on,Kuala Lumpur, Aug. 2015, pp. 19-24. [IEEExplore]

BOOK CHAPTERS

  • X. Mo, N. Wary, and A. Chan Carusone, “High-Performance CMOS Clock Distribution,”  in Phase-Locked Frequency Generation and Clocking: Architectures and circuits for modern wireless and wireline systems, Editor W. Rhee, The Institution of Engineering and Technology, 2020. [Link]

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