Nijwm Wary

Skip to content
  • home
  • Publications
  • Chip Gallery
  • Teaching
  • Group
  • Projects
Search

Mixed Signal VLSI Design (Spring 2025)

  • SAR ADC Basic Architecture
  • Charge Redistribution Based SAR ADC
  • Pipeline ADC Basic Architecture
  • 1.5 bit per stage Pipeline ADC

Assignments

  • Assignment-1 (DAC ADC). Submission Link. [Last date 26-04-25]
  • Assignment-2 (DAC ADC) Submission Link [Last date 05-05-25]
  • Assignment PLL. Submission Link [Last date 05-05-25]

Share this:

  • Share on X (Opens in new window) X
  • Share on Facebook (Opens in new window) Facebook
Like Loading...
Create a website or blog at WordPress.com
    • Nijwm Wary
    • Sign up
    • Log in
    • Copy shortlink
    • Report this content
    • Manage subscriptions
%d