• Experiment 1: Introduction to Logic Gates
  • Manual
  • Datasheets: 7400 7402 7408 7432
  • Logisim Tutorial Video
  • Logisim Installation files
  • Report Submission link (Deadline: 26th January,2021)

• Experiment 2: Binary addition and subtraction using Logic Gates
  • Manual
  • Report Submission Link (Deadline: 2:30 PM, 9th February, 2021)

• Experiment 3: Design of Combinational Logic Circuits
  • Manual
  • Report Submission Link (Deadline: 15th February, 2021)

• Experiment 4: Code Converters
  • Manual
  • Report Submission Link (Deadline: 22rd February, 2021)

• Experiment 5: 4-bit Adders and Decoders
  • Manual
  • Report Submission Link (Deadline: 1st March, 2021)
• Experiment 6: Latches and Flip-Flops
  • Manual
  • Report Submission Link (Deadline: 30th March, 2021)
• Experiment 7: 7-segment, D-Latch and D-FF.
  • Manual
  • Timing Analysis of D-Latch in Logisim
  • Report Submission Link (Deadline: 30th March, 2021)
• Experiment 8: Registers
  • Link for submission
• Experiment 9: Introduction to Verilog and implementation of 4-bit adder
  • Manual
  • Modelsim installation tutorial
  • Modelsim demonstrations
  • Modelsim demonstration with testbench. (PPT)
  • Report Submission Link

Tutorial Videos

• Trainer Kit Video tutorial